Evatronix Standardizes on TransEDA for IP Quality Excellence

Los Gatos, Calif. (USA) - February 20, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions, today announced that Evatronix S.A. has standardized on TransEDA's Verification Navigator integrated design verification environment as a vital part of its intellectual property (IP) quality assurance policy. Evatronix is a leading provider of IP and design services.

"Leading IP consumers trust Evatronix to provide reliable and verified design cores, so quality assurance is our number one priority," said Wojciech Sakowski, vice president of Evatronix. "Our decision to invest in TransEDA's tools is already proving extremely valuable. With our previous methodology, we performed extensive simulations and rigorous prototype testing, but we weren't completely confident that the results were bug-free. TransEDA has greatly improved our confidence using much less time and effort."

Tom Borgstrom, vice president of marketing at TransEDA said, "The demand for high quality IP from suppliers such as Evatronix continues to rise. Additionally, the larger semiconductor and system houses are making proven IP qualification a mandatory requirement when selecting third-party IP. TransEDA's verification tools provide companies like Evatronix with significant advantages in reaching quality goals. By setting coverage standards and improving code quality, we can help Evatronix and other IP vendors deliver first-rate IP that their customers can trust."

Verification Speeds IP Core Development and Improves Quality
Evatronix has defined and implemented a new verification plan as part of its IP design and qualification process. It relies on the TransEDA Verification Navigator product suite for coverage analysis, hardware description language (HDL) and design rule checking, and test suite analysis. TransEDA's VN-Cover™ coverage analysis solution helps Evatronix measure the effectiveness of the test suite developed for a particular core. Its ease-of-use enables the creation and enforcement of stringent corporate goals for coverage of all possible conditions by the test suite.

"We used VN-Cover on our CZ80sio project to improve the test suite and meet our 100 percent statement, 100 percent branch, and 90 percent condition coverage standards. VN-Cover immediately proved its worth by revealing a new bug," said Miroslaw Bandzerewicz, quality assurance manager at Evatronix. "We used VN-Check™ configurable HDL checker for the static verification of HDL code quality and design rule compliance. In addition to verification, it also partially automated rating cores against industry standard reusability rules, helping us to better comply with these important objectives."

Evatronix has also adopted the TransEDA VN-Optimize™ test suite analysis tool, which reduces verification time by optimizing the test suite to achieve coverage goals with the fewest number of tests. "We used to perform full core verification after every code change, but this took much too long," said Adam Bitniok, project manager of a math coprocessor design. "VN?Optimize helps us do just the right amount of testing. With our C80187 coprocessor project, we went from 3,368 test sets to 212, with just a four percent drop in coverage."

About Evatronix
Established as an early reseller of CAD and EDA systems, Evatronix S.A. is principally a developer of electronic virtual components (IP cores). Sold primarily through the distribution network of American partner CAST, Inc. (www.cast-inc.com), the company's line of IP cores features 8- and 16-bit processors compatible with the Intel® 8051, Motorola® 68000, and TI® TMS320C25 digital signal processor; controllers for the I2C, SDLC & USB standards; and a variety of other standards-based and popular functions. The company recently introduced electronic design services, including front-end ASIC design (VHDL & Verilog modeling), FPGA design (for Altera & Xilinx technologies) and the development of hardware and software for embedded systems.

Evatronix is focused on engineering excellence, and three quarters of its employees are full-time design engineers. Company headquarters are in Bielsko-Biala, Poland, and the main development center is located in Gliwice, Poland. More information can be found at the company's website: www.evatronix.pl.

About TransEDA
TransEDA PLC (symbol TRA on the Alternative Investment Market in London) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models for advanced microprocessors and bus interfaces.

TransEDA's design verification software performs application-specific test automation, configurable HDL checking, code and finite state machine (FSM) coverage analysis and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the world's top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, Calif. 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, e-mail: info@transeda.com.

Note: TransEDA is a registered trademark and Verification Navigator, VN-Check, VN-Cover, and VN-Optimize are trademarks of TransEDA. All other trademarks are properties of their respective holders.

MEDIA CONTACTS:

In North America, Asia & Japan:
TransEDA
Tom Borgstrom
(408) 335-1303
tom.borgstrom@transeda.com

Armstrong Kendall, Inc.
Jen Bernier
408) 975-9863
jen@akipr.com

In the U.K. and Europe:
Pentacom
Sharon Graves
+44 1242 525205
sharon.graves@pentacomagency.com

Evatronix
Wojciech Sakowski
+48 32 231 11 71
wojtek@gliwice.evatronix.com.pl